Solar cell texturing is an important process step that improves light trapping performance and increases overall efficiency.
Currently, mono-crystalline wafers are textured using KOH etchants that form pyramidal structures. These structures formed along crystal planes result in very good light trapping properties.
On the other hand, multi-crystalline-Si (mc-Si) wafers have to be isotropically etched. For multi-crystalline wafers, an industry-standard isotexture process is used that involves etching the entire wafer surface using a suitable etchant, typically an HF/Nitric/Acetic Acid mixture. The isotexture process utilizes the irregularity of the kerf damage to roughen the surface.
Although the isotexture process is cost effective, the resulting isotextured surface is far from optimal compared to patterned features. The textured surfaces have improved light trapping properties but are less effective than pyramidal or trough structures. According to an NREL/1366 report, using a trough structure, an absolute efficiency improvement of 0.3% has been calculated compared to an isotextured surface. Additionally, with the best light trapping structures (random pyramids), up to 0.8% absolute efficiency increase can be achieved.
An alternative to the isotexture process involves printing an etch mask on the mc-Si wafer, and then etching the wafer regions exposed through the mask to form patterned light trapping features. However, traditional mask printing techniques such as ink jet, screen printing or flexography can't meet the minimum linewidth specs, and newer techniques such as micro contact printing, dip pen nanolithography (DNP, using AFM-type probes as write tips) or other MEMS approaches are too slow, fragile or don't provide sufficient vertical clearance over large areas.
What is needed is a cost-effective method for generating patterned pyramid or trough features in multi-crystalline wafers that avoids the problems associated with conventional methods.